221 lines
5.3 KiB
C
221 lines
5.3 KiB
C
/*
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* Copyright (C) 2010-2014 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#ifndef __LINUX_REGULATOR_MAX17135_H_
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#define __LINUX_REGULATOR_MAX17135_H_
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/*
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* PMIC Register Addresses
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*/
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enum {
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REG_MAX17135_EXT_TEMP = 0x0,
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REG_MAX17135_CONFIG,
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REG_MAX17135_INT_TEMP = 0x4,
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REG_MAX17135_STATUS,
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REG_MAX17135_PRODUCT_REV,
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REG_MAX17135_PRODUCT_ID,
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REG_MAX17135_DVR,
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REG_MAX17135_ENABLE,
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REG_MAX17135_FAULT, /*0x0A*/
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REG_MAX17135_HVINP,
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REG_MAX17135_PRGM_CTRL,
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REG_MAX17135_TIMING1 = 0x10, /* Timing regs base address is 0x10 */
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REG_MAX17135_TIMING2,
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REG_MAX17135_TIMING3,
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REG_MAX17135_TIMING4,
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REG_MAX17135_TIMING5,
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REG_MAX17135_TIMING6,
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REG_MAX17135_TIMING7,
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REG_MAX17135_TIMING8,
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};
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#define MAX17135_REG_NUM 21
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#define MAX17135_MAX_REGISTER 0xFF
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/*
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* Bitfield macros that use rely on bitfield width/shift information.
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*/
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#define BITFMASK(field) (((1U << (field ## _WID)) - 1) << (field ## _LSH))
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#define BITFVAL(field, val) ((val) << (field ## _LSH))
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#define BITFEXT(var, bit) ((var & BITFMASK(bit)) >> (bit ## _LSH))
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/*
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* Shift and width values for each register bitfield
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*/
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#define EXT_TEMP_LSH 7
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#define EXT_TEMP_WID 9
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#define THERMAL_SHUTDOWN_LSH 0
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#define THERMAL_SHUTDOWN_WID 1
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#define INT_TEMP_LSH 7
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#define INT_TEMP_WID 9
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#define STAT_BUSY_LSH 0
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#define STAT_BUSY_WID 1
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#define STAT_OPEN_LSH 1
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#define STAT_OPEN_WID 1
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#define STAT_SHRT_LSH 2
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#define STAT_SHRT_WID 1
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#define PROD_REV_LSH 0
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#define PROD_REV_WID 8
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#define PROD_ID_LSH 0
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#define PROD_ID_WID 8
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#define DVR_LSH 0
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#define DVR_WID 8
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#define ENABLE_LSH 0
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#define ENABLE_WID 1
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#define VCOM_ENABLE_LSH 1
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#define VCOM_ENABLE_WID 1
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#define FAULT_FBPG_LSH 0
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#define FAULT_FBPG_WID 1
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#define FAULT_HVINP_LSH 1
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#define FAULT_HVINP_WID 1
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#define FAULT_HVINN_LSH 2
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#define FAULT_HVINN_WID 1
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#define FAULT_FBNG_LSH 3
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#define FAULT_FBNG_WID 1
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#define FAULT_HVINPSC_LSH 4
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#define FAULT_HVINPSC_WID 1
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#define FAULT_HVINNSC_LSH 5
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#define FAULT_HVINNSC_WID 1
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#define FAULT_OT_LSH 6
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#define FAULT_OT_WID 1
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#define FAULT_POK_LSH 7
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#define FAULT_POK_WID 1
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#define HVINP_LSH 0
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#define HVINP_WID 4
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#define CTRL_DVR_LSH 0
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#define CTRL_DVR_WID 1
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#define CTRL_TIMING_LSH 1
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#define CTRL_TIMING_WID 1
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#define TIMING1_LSH 0
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#define TIMING1_WID 8
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#define TIMING2_LSH 0
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#define TIMING2_WID 8
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#define TIMING3_LSH 0
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#define TIMING3_WID 8
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#define TIMING4_LSH 0
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#define TIMING4_WID 8
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#define TIMING5_LSH 0
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#define TIMING5_WID 8
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#define TIMING6_LSH 0
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#define TIMING6_WID 8
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#define TIMING7_LSH 0
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#define TIMING7_WID 8
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#define TIMING8_LSH 0
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#define TIMING8_WID 8
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struct max17135 {
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/* chip revision */
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int rev;
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struct device *dev;
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struct max17135_platform_data *pdata;
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/* Platform connection */
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struct i2c_client *i2c_client;
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/* Timings */
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unsigned int gvee_pwrup;
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unsigned int vneg_pwrup;
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unsigned int vpos_pwrup;
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unsigned int gvdd_pwrup;
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unsigned int gvdd_pwrdn;
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unsigned int vpos_pwrdn;
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unsigned int vneg_pwrdn;
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unsigned int gvee_pwrdn;
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/* GPIOs */
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int gpio_pmic_pwrgood;
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int gpio_pmic_vcom_ctrl;
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int gpio_pmic_wakeup;
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int gpio_pmic_v3p3;
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int gpio_pmic_intr;
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/* MAX17135 part variables */
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int pass_num;
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int vcom_uV;
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/* One-time VCOM setup marker */
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bool vcom_setup;
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/* powerup/powerdown wait time */
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int max_wait;
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};
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enum {
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/* In alphabetical order */
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MAX17135_DISPLAY, /* virtual master enable */
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MAX17135_GVDD,
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MAX17135_GVEE,
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MAX17135_HVINN,
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MAX17135_HVINP,
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MAX17135_VCOM,
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MAX17135_VNEG,
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MAX17135_VPOS,
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MAX17135_V3P3,
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MAX17135_NUM_REGULATORS,
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};
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/*
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* Declarations
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*/
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struct regulator_init_data;
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struct max17135_regulator_data;
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struct max17135_platform_data {
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unsigned int gvee_pwrup;
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unsigned int vneg_pwrup;
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unsigned int vpos_pwrup;
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unsigned int gvdd_pwrup;
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unsigned int gvdd_pwrdn;
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unsigned int vpos_pwrdn;
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unsigned int vneg_pwrdn;
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unsigned int gvee_pwrdn;
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int gpio_pmic_pwrgood;
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int gpio_pmic_vcom_ctrl;
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int gpio_pmic_wakeup;
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int gpio_pmic_v3p3;
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int gpio_pmic_intr;
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int pass_num;
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int vcom_uV;
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/* PMIC */
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struct max17135_regulator_data *regulators;
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int num_regulators;
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};
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struct max17135_regulator_data {
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int id;
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struct regulator_init_data *initdata;
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struct device_node *reg_node;
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};
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int max17135_reg_read(int reg_num, unsigned int *reg_val);
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int max17135_reg_write(int reg_num, const unsigned int reg_val);
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#endif
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